1. Field of the Invention
The present invention relates to a memory cell unit, a nonvolatile semiconductor storage device including such a memory cell unit, and a memory cell array driving method.
2. Description of the Related Art
Exemplary memory cells of a known EEPROM are of a MOS transistor structure, which includes a gate portion including a charge storage layer and a control gate and is adapted to inject electric charges into the charge storage layer and release the electric charges from the charge storage layer by utilizing a tunnel current. The memory cells each store data “0” and “1” on the basis of a difference in threshold voltage attributable to a difference in the charge storage state of the charge storage layer.
In the case of an n-channel memory cell having a floating gate as the charge storage layer, for example, a positive high voltage is applied to the control gate with source and drain diffusion layers and a substrate being grounded for the injection of electrons into the floating gate. At this time, the electrons are injected into the floating gate from the substrate by the tunnel current. Thus, the threshold voltage of the memory cell is positively shifted by the injection of the electrons. For the release of the electrons from the floating gate, on the other hand, a negative voltage is applied to the control gate with the source and drain diffusion layers and the substrate being grounded. At this time, the electrons are released from the floating gate to the substrate by the tunnel current. Thus, the threshold voltage of the memory cell is negatively shifted by the release of the electrons. In the aforesaid operation, a relationship between a floating gate/control gate coupling capacitance and a floating gate/substrate coupling capacitance is important for efficiently achieving the electron injection and the electron release, i.e., for the writing and the erasing. In other words, as the capacitance between the floating gate and the control gate is increased, the potential of the control gate can more effectively be transferred to the floating gate, thereby facilitating the writing and the erasing.
With the recent progress of the semiconductor technology, particularly the micro-processing technique, the size reduction and capacity increase of memory cells of EEPROMs are rapidly promoted. Therefore, how to reduce the area of the memory cells and how to increase the capacitance between the floating gate and the control gate are critical issues. In order to increase the capacitance between the floating gate and the control gate, it is necessary to reduce the thickness of a gate insulation film provided between the floating gate and the control gate, to increase the dielectric constant of the gate insulation film, or to increase the area of opposed surfaces of the floating gate and the control gate. However, the thickness reduction of the gate insulation film has limitation in consideration of the reliability. A conceivable approach to the increase of the dielectric constant of the gate insulation film is to employ a silicon nitride film or the like instead of a silicon oxide film. However, this approach poses a problem associated with the reliability and, hence, is not practical. Therefore, it is necessary to increase an overlap between the floating gate and the control gate to not smaller than a predetermined area in order to provide a sufficient capacitance. However, this is obstructive to the reduction of the area of the memory cells for the increase of the storage capacity of the EEPROM. Hence, there is a demand for means for achieving both the reduction of the memory cell area and the increase of the capacitance between the floating gate and the control gate.
There is known an EEPROM including a plurality of memory cell units, as shown in FIG. 18, which each include two memory cells provided on a column-shaped semiconductor layer 12 and selection transistors disposed above and below the memory cells (see, for example, Japanese Unexamined Patent Publication No. Hei 4-79369 (1992)). The memory cells are constructed by utilizing a peripheral wall of each of column-shaped semiconductor layers arranged in a matrix configuration and isolated from each other by a lattice trench formed in a semiconductor substrate. That is, the memory cell units each include a drain diffusion layer 7 provided in an upper surface of the column-shaped semiconductor layer, a common source diffusion layer 11 provided in a bottom of the trench, and charge storage layers 1, 3 and control gates 2, 4 entirely surrounding the peripheral wall of the column-shaped semiconductor layer. Control gate lines are each provided by sequentially connecting control gates provided around column-shaped semiconductor layers serially arranged in one direction. Bit lines are each connected to drain diffusion layers of memory cell units sequentially arranged as crossing the control gate lines. Where the memory cells each have a one-transistor-per-cell structure, a cell current flows into unselected cells (or a reading error occurs) if the memory cells are over-erased with a read potential of 0V and a negative threshold voltage. To assuredly prevent this phenomenon, the selection transistors are disposed in series to the memory cells in upper and lower portions of the column-shaped semiconductor layer with gate electrodes 5, 6 thereof at least partly surrounding the peripheral surface of the column-shaped semiconductor layer.
Thus, the memory cells of the conventional EEPROM each include the charge storage layer and the control gate formed as surrounding the column-shaped semiconductor layer by utilizing the peripheral wall of the column-shaped semiconductor layer. Therefore, the capacitance between the charge storage layer and the control gate can sufficiently be increased with a smaller memory cell area. Further, the drain diffusion layers of the memory cell units connected to the bit lines are respectively provided in the upper surfaces of the column-shaped semiconductor layers, and electrically isolated from each other by the trench. Thus, a device isolation area can be reduced, thereby further reducing the memory cell size. Therefore, it is possible to provide large storage capacity memory cell units in which memory cells each having an excellent writing/erasing efficiency are integrated.
It is herein assumed that plural memory cells connected in series on each of the column-shaped semiconductor layers have the same threshold voltage. Here, a reading operation is performed by applying a read potential to control gates (CG) of the memory cells for determination of “0” or “1” depending on the presence or absence of an electric current. If the electric current flowing through the semiconductor layer causes a potential difference between the memory cells located at opposite ends of the serial memory cell arrangement on the single semiconductor layer due to a resistant component of the semiconductor layer, the potential difference makes the threshold voltages of the respective memory cells non-uniform (back bias effect). This enhances fluctuation in the threshold voltages. The back bias effect limits the number of memory cells to be connected in series on the device, thereby posing a problem associated with the increase of the storage capacity. Further, the back bias effect may occur not only where the plural memory cells are connected in series on the single column-shaped semiconductor layer, but also where a single memory cell is provided on the single column-shaped semiconductor layer. That is, the threshold voltages of the respective memory cells are liable to be non-uniform due to variation in an in-plane back bias effect of the semiconductor substrate. The variations in the threshold voltages depending on the positions of the memory cells adversely influence write/erase/read voltages to be applied for the writing, erasing and reading operations with respect to the memory cells. Hence, there is a demand for a solution to the problem associated with the back bias effect of the substrate.
On the other hand, there is also known a memory cell unit in which a column-shaped semiconductor layer is electrically isolated from a semiconductor substrate as shown in FIG. 19 (see, for example, Japanese Unexamined Patent Publication No. 2002-57231). By thus electrically isolating the column-shaped semiconductor layer from the semiconductor substrate, the back bias effect can be suppressed. Therefore, a memory cell unit having an improved integration density can be provided, in which the coupling ratio of the floating gate/control gate coupling capacitance is further increased without increasing the area of the memory cells, and the variations in cell characteristics attributable to the production process are suppressed.
When a writing operation is performed in a semiconductor storage device including memory cell units each having the aforesaid construction, a high writing prevention voltage is applied to bit lines not subjected to the writing operation. In general, the memory cell units are arranged longitudinally and transversely in a matrix configuration in the semiconductor storage device. Control gates of memory cells provided in memory cell units (column-shaped semiconductor layers) arranged longitudinally in each column of the matrix configuration are connected commonly to corresponding control gate lines, and selection gates of selection transistors provided in memory cell units (column-shaped semiconductor layers) arranged longitudinally in each column of the matrix configuration are connected commonly to corresponding selection gate lines. Drain diffusion layers provided in memory cell units (column-shaped semiconductor layers) arranged transversely in each row of the matrix configuration are connected commonly to a bit line. When a writing operation is performed on a selected memory cell in this memory cell unit array, electrons are injected into the selected memory cell by applying a positive writing voltage to a control gate line connected to the control gate of the selected memory cell, applying a grounding voltage or a positive voltage to a source diffusion layer and applying a grounding voltage to a drain diffusion layer of the memory cell unit including the selected memory cell. At this time, a channel formed below a selection gate of a selection transistor adjacent to the drain diffusion layer is electrically connected to a channel formed below a control gate of a memory cell adjacent to the selection transistor, so that the potentials of the channels are virtually equalized with the grounding voltage applied to the drain diffusion layer. Further, the writing to unselected memory cells which share the control gate line with the selected memory cell is prevented by applying a positive writing prevention voltage to bit lines connected to memory cell units not including the selected memory cell. Where the selected memory cell is a memory cell disposed closest to the source diffusion layer in the memory cell unit, a sufficiently high voltage is applied to control gates of memory cells disposed on an upper side of the selected memory cell and the selection gate of the selection transistor adjacent to the drain diffusion layer for the electron injection from the drain diffusion layer. Therefore, the same voltage is applied to control gates and selection gates in the memory cell units not including the selected memory cells which share the control gate line and the selection gate line with the selected memory cell. If this voltage is sufficiently high, the channel formed below the selection gate adjacent to the drain diffusion layer is electrically connected to the channel formed below the control gate of the memory cell adjacent to the selection gate. Therefore, the potentials of the channels are virtually equalized with the positive writing prevention voltage applied to the drain diffusion layer via the bit line. Thus, the electron injection to charge storage layers of the unselected memory cells is prevented, because a potential difference between the charge storage layers and the control gates to which the writing voltage is applied is sufficiently small. Then, the potential of an impurity diffusion layer disposed between the lowermost memory cell and the selection transistor adjacent to the source diffusion layer is virtually equalized with the writing prevention voltage.
However, if the selection transistor adjacent to the source diffusion layer has a breakdown voltage lower than the bit line writing prevention voltage, an electric current flows into the channel formed below the gate electrode even with the selection transistor being off. This results in breakdown of the selection transistor. As a result, the voltage (inter-channel voltage) of the impurity diffusion layer between the lowermost memory cell and the selection transistor adjacent to the source diffusion layer with respect to the source diffusion layer is reduced to a level equivalent to the breakdown voltage of the source side selection transistor (which is lower than the bit line writing prevention voltage). Therefore, the channel potential of the lowermost memory cell is reduced. Hence, there is a possibility that a writing error occurs on the charge storage layer of the memory cell due to the voltage difference between the source side selection transistor and the control gate.
In order to prevent the writing error due to the insufficient breakdown voltage of the selection transistor, the voltage applied to the source diffusion layer should be stabilized, and the source side selection transistor should have a sufficient breakdown voltage with respect to the writing prevention voltage. This is because the potential of the impurity diffusion layer is equivalent to the sum of the voltage of the source diffusion layer with respect to the grounding potential and the voltage of the selection transistor between the source diffusion layer and the impurity diffusion layer.
Where a positive source voltage is applied to the source diffusion layer, the stability of the voltage of the source diffusion layer is influenced by the breakdown voltage of the selection transistor of the memory cell unit including the selected memory cell. As described above, the potential of the channel of the selected memory cell is virtually equivalent to the grounding voltage applied to the drain diffusion layer, so that the potential of the adjacent impurity diffusion layer is equivalent to the channel potential. Therefore, if the breakdown voltage of the selection transistor between the impurity diffusion layer and the source diffusion layer is lower than the source voltage, the breakdown occurs, so that the voltage of the source diffusion layer with respect to the grounding voltage is reduced to the level equivalent to the breakdown voltage of the source side selection transistor. Therefore, the voltages of the source diffusion layers of the other memory cell units which share the selection gate line are also reduced to the level equivalent to the breakdown voltage.
In general, the breakdown voltage of a minute transistor is determined by a minimum distance between a source and a drain disposed on opposite sides of a channel of the transistor. Therefore, the breakdown voltage of the aforesaid selection transistor is determined by a minimum distance between the source diffusion layer and the impurity diffusion layer disposed between the lowermost memory cell and the selection transistor. Hence, the breakdown voltage of the transistor can be increased by sufficiently increasing the inter-channel distance. However, the increase of the inter-channel distance means that the column-shaped semiconductor layers should be formed as having a greater height. This means that a semiconductor layer should be formed as having a greater thickness and unnecessary portions of the semiconductor layer should be removed to a greater depth for formation of the column-shaped semiconductor layers in a semiconductor device production process. Therefore, the semiconductor device production process is time-consuming, resulting in cost increase. Hence, it is not preferred to unreasonably increase the inter-channel distance.
Another method for allowing the selection transistor to have a breakdown voltage sufficient for the driving of the memory cell array is to give consideration to the construction of the selection transistor. Further, consideration may be given to a memory cell array driving method in the writing operation.